Design and Implementation of a CCSDS Image Compression Core Based on FPGA

Taking full consideration of algorithm characteristics and the implementation platform, novel encoding control logic and data organization structures have been devised. To address the performance bottleneck in the scanning and encoding process, a fully parallel scanning plus adaptive parallel encoding method has been proposed, significantly enhancing the compression core's throughput.

Focusing on the key metric of compression efficiency, a compression architecture with a segment size of 256 has been designed, achieving better compression results at the same compression ratio. By implementing a segmented compression mechanism, the prevention of error propagation has been realized, and support for real-time quality control and progressive transmission has been provided. The compression core supports images with a maximum size of 4096x4096 pixels and a maximum bit depth of 16 bits.