Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures

At the circuit-layer, this thesis investigates the root causes of timing errors and proposes a framework that isolates the timing critical paths to a single pipeline stage. At microarchitecture-layer, a dynamic cycle adjustment technique is devised to prevent timing errors in case of excitation of a timing critical path. At application/software-layer, the concept of approximate computing is leveraged to minimise timing errors.

In the second part, two accurate timing error modeling and evaluation frameworks are proposed; for the first time the instruction execution history (i.e., type and order of instructions within a pipeline at any instant) is considered. DEFCON, a fully automated framework which customises a genetic algorithm driven by accurate dynamic timing analysis to stochastically search for microarchitecture-aware instructions that trigger timing errors, is presented.

ARETE is then derived, a novel framework that enables fully-accurate impact-evaluation of timing errors on applications by combining dynamic binary instrumentation with machine learning-guided dynamic timing analysis.<br><br>Finally, the inherent complex dynamic timing behaviour of pipelined architectures is exploited and a low power security primitive for hardware-rooted device authentication is proposed. To achieve this, DTA-PUF, a novel lightweight physical unclonable function, is introduced.