GDSII and OASIS Design Files for the TypeOneBIS Biogenic Replicator — a programmable universal molecular constructor — 2-mer and 16-mer chips v1.01

The C-section’s purpose is to provide for low cross-contamination between the loading of successive slug.</p><p dir="ltr">The designs are governed by the TypeOneBIS Community License (TCL). Layer 4 of each design contains a vectorized copy of the TCL notice. Opening or using the design constitutes acceptance of the TCL in full.

The design files are not for fabrication without accepting the TypeOneBIS Community License.</p><p dir="ltr">This dataset is a companion to the TypeOneBIS Biogenic Replicator Platform White Paper and the <b>TypeOneBIS Community License (TCL)</b>. Both are cross-linked in the Related Identifiers below.</p><p><br></p><h3 dir="ltr"><b><u>TECHNICAL REPLICATOR DETAILS</u></b></h3><p dir="ltr"><b><u>The 2-mer </u></b><b><u>Baseline</u></b><b><u> </u></b><b><u>Chip</u></b><b>.</b> A four (4)-core base replicator chip designed for 4-inch silicon wafers.

Each core is independent, and contains two (2) serpentine chambers, which are sequentially loaded via <b>one</b> serial Pulse Width Modulated (PWM) input line. The 2 serpentine chambers constitute the first stage inputs of the hierarchical merge matrix. This replicator-chip can be used to validate the merge matrix, the capillary stop valve diodes, the Quake valve architecture, the PWM serial loading system with C-section bypass-flush, the serpentine additive reaction chambers, the alignment marks, the inter-core transfer protocol, the optical total internal reflection (TIR), the optical transport, the pneumatic transport, the flow rates, optical <b>nlock/plock</b> addition reactions, nlock/plock ligase reactions, nlock/plock binding <b>on-off</b> times, scaffolding anti-aggregation mechanics, etc.

This baseline chip, is intended for process and architecture characterization. However, it is a fully functional replicator which can be daisy-chained or parallelized to produce mega-mer molecules (<i>see the 16-mer section below</i>).</p><p dir="ltr"><b><u>The 16-mer Industrial </u></b><b><u>Chip</u></b><b>.</b> A two (2)-core replicator chip designed for 6-inch silicon wafers. Each core is independent, and contains sixteen (2 x 8 – input segments) serpentine chambers, which are sequentially loaded via the two (2) serial PWM input line – one line to each 8-serpentine segment.

The 16 serpentine chambers constitute the first stage inputs of the hierarchical merge matrix. This is an industrial replicator chip, intended for production of sequence-defined molecules at scale.</p><p dir="ltr">The 16-mer replicator is not limited to producing only 16-mers. It is the first <b>rung</b> of a scalable <b>rack</b> based architecture.

By daisy-chaining copies of the same chips, the platform scales without bound, and without any change to the chip design.</p><p dir="ltr">The scaling mechanism is facilitated by serial PWM loading between cores and between chips. The output of one merge matrix core, becomes the input of the next downstream merge matrix core. The input-molecular <b>scaffolds</b> are serially PWM loaded into the 16 serpentine chambers of the core’s input first-stage via the two (2) C-section bypass-flush rail when each upstream output becomes available.</p><p dir="ltr">Molecular scaffolds (monomer or multi-mer) are loaded into the core’s serpentine chambers as individual <b>contiguous slug</b> packages.

Each slug package is separated by a <b>gas spacer</b>, e.g. nitrogen. A typical slug length is <b>~</b><b>3</b><b>6</b><b>mm</b>, while the <b>inter-slug</b> gas (nitrogen) spacer length is <b>~</b><b>11mm</b> – where each slug (or spacer) is <b>100µm</b> wide.<br><br></p><p dir="ltr"><b><u>The </u></b><b><u>daisy-chain </u></b><b><u>scaling path </u></b><b><u>is :</u></b></p><p dir="ltr"><b><i>S</i></b><b><i>caling path requires </i></b><b><i>only 2</i></b><b><i> chips!</i></b></p><p dir="ltr"><b>1. 16-mer :</b></p><p dir="ltr">One 16-channel merge matrix core produces a single 16-mer from 16 monomer <b>slug</b> inputs.

This is the base operation.</p><p dir="ltr"><b>2. 256-mer:</b></p><p dir="ltr">16 distinct 16-mer <b>slugs</b> are serially PWM loaded into a downstream merge matrix core. The matrix core merges them into one 256-mer.</p><p dir="ltr"><b>3. 4,096-mer:</b></p><p dir="ltr">16 distinct 256-mer <b>slugs</b> are serially PWM loaded into the next downstream merge matrix core. The matrix core then merges them into one 4,096-mer.</p><p dir="ltr"><b>4. 65,536-mer (64k-mer):</b></p><p dir="ltr">16 distinct 4,096-mer <b>slugs</b> are serially PWM loaded into the next downstream merge matrix core.

The matrix merges them into the final 65,536-mer.</p><p dir="ltr">The merge matrix in every core is identical. The only difference between levels is what <b>slug</b> is loaded into the first-stage serpentine input chambers. The same chip family scales from a single 16-mer to a 64k-mer with no design change.

Because this process is serial and slow it could take a few days to complete the cycle, but importantly the cycle can be operated continuously.</p><p dir="ltr"><b>Importantly</b>, because no synchronization is required between loading serpentines, even in the <b>same</b> segment, an upstream replicator core can be used to produce each <b>multi-mer</b>, <b>one</b><b>-at-a-time</b>, which is then loaded into each downstream serpentine when it is produced.<br><br></p><p dir="ltr"><b><u>The </u></b><b><u>parallel</u></b><b><u> </u></b><b><u>scaling path is:</u></b><br><b><i>S</i></b><b><i>caling path requires </i></b><b><i>2,185</i></b><b><i> chips!</i></b></p><table><tr><th><p dir="ltr">Layer</p></th><th><p dir="ltr">Chips</p></th><th><p dir="ltr">Cores</p></th><th><p dir="ltr">PWM I/O</p></th><th><p dir="ltr">Input per core</p></th><th><p dir="ltr">Total inputs</p></th><th><p dir="ltr">Outputs</p></th><th><p dir="ltr">Output length</p></th></tr><tr><td><p>1</p></td><td><p>2,048</p></td><td><p>4,096</p></td><td><p>8,192</p></td><td><p dir="ltr">16 monomers</p></td><td><p>65,536</p></td><td><p>4,096</p></td><td><p dir="ltr">16-mer</p></td></tr><tr><td><p>2</p></td><td><p>128</p></td><td><p>256</p></td><td><p>512</p></td><td><p dir="ltr">16 × 16-mer</p></td><td><p>4,096</p></td><td><p>256</p></td><td><p dir="ltr">256-mer</p></td></tr><tr><td><p>3</p></td><td><p>8</p></td><td><p>16</p></td><td><p>32</p></td><td><p dir="ltr">16 × 256-mer</p></td><td><p>256</p></td><td><p>16</p></td><td><p dir="ltr">4,096-mer</p></td></tr><tr><td><p>4</p></td><td><p>1</p></td><td><p>1</p></td><td><p>2</p></td><td><p dir="ltr">16 × 4,096-mer</p></td><td><p>16</p></td><td><p>1</p></td><td><p dir="ltr">65,536-mer</p></td></tr></table><p dir="ltr"><br><b>1. 65,536 </b><b>monomer input </b><b><u>s</u></b><b><u>lugs</u></b><b> :</b></p><p dir="ltr">This first layer requires 2,048-individual chips, containing 4,096 cores.

Since each chip contains two (2)-cores, then 32-monomer (or multi-mer) <b>slugs</b> are loaded into each chip. Each core is serially PWM loaded, and there are 2 PWM loading lines per core. As a result, the first layer has 8,192 independent loading lines.

Each core is loaded independently and no timing synchronization is required during PWM loading of the cores. The transfer of the input serpentine <b>slugs</b> to the next stage occurs via a dual-input same-sided, coupled CSV diode, and each core-stage has its own loading and operations control quake values. Transfers to stage-2 of each core is controlled independently.

Each core also has it own independent output control, so transfer to the next downstream layer of chips does not require temporal synchronization. This facilitates continuous operation cycles.</p><p dir="ltr"><b>2</b><b>. </b><b>4,096</b><b> - </b><b>16-mer</b><b> input </b><b><u>s</u></b><b><u>lugs</u></b><b> </b><b>fr</b><b>om</b><b> upstream layer</b><b> :</b></p><p dir="ltr">This second layer requires 128-chips and this provides for 512 serial loading PWM input lines.

Sixteen (16), 16-mer are loaded into each core, for a total of 4096 16-mers. This layer of chips produce 256 outputs for the next chip layer.</p><p dir="ltr"><b>3</b><b>. </b><b>256</b><b> - </b><b>256</b><b>-mer</b><b> input </b><b><u>s</u></b><b><u>lugs</u></b><b> </b><b>fr</b><b>om</b><b> upstream layer</b><b> :</b></p><p dir="ltr">This third layer requires 8-chips and this provides for 32 serial loading PWM input lines.

Sixteen (16) 256-mer are loaded into each core, for a total of 256 16-mers. This layer of chips produce 16 outputs for the next chip layer.</p><p dir="ltr"><b>4</b><b>. </b><b>16</b><b> - </b><b>4096</b><b>-mer</b><b> input </b><b><u>s</u></b><b><u>lugs</u></b><b> </b><b>fr</b><b>om</b><b> upstream layer</b><b> :</b></p><p dir="ltr">This fourth layer requires 1-chip, and uses only 1-core of that chip. This provides for 2 serial loading PWM input lines.

Sixteen (16) 4096-mer are loaded into this core. This chip, using only 1 core produces the final <b>65,536-mer </b>molecule as its output.</p><p dir="ltr"><br><b>The 65,536-mer requires only 16 merge stages in total.</b></p><p dir="ltr">Applying the yield equation <b>Y=P</b><b>^</b><b>n with 98% per-stage purity</b>:</p><p dir="ltr"><b>Yield (Y)</b><b> = .98 ^ 16 = ~0.7238.</b></p><p dir="ltr"><b>The result is ~72.4% yield purity for a 65,536-mer molecule !</b></p><p dir="ltr">A 65,536-mer is produced at approximately 72.4% yield purity.

This is the consequence of the logarithmic merge matrix architecture. The same molecule produced by linear synthesis would require 65,535 sequential steps, at which point the yield purity is effectively zero.</p><p dir="ltr">A crucial point is, as the associated white paper states, the reactions in the chamber are <b>not</b> protein or peptide reactions. They are optical <b>nlock/plock</b> chain <b>addition</b> reactions.

Thus the end result molecule is a scaffold chain. Because the scaffold is optimized for the replicator, it is engineered to completely avoid aggregation and remain completely linear during the whole process.</p><p dir="ltr">The final scaffolding chain can then be processed using the desired molecular scissor chemistry to excise and join the passenger molecules.</p><p dir="ltr">While the scissor chemistry could be done on chip, it may be more efficient to perform this process in a separate specialized fluidics chip or other device.

The output of each core in a chip, can be further processed and purified before being passed into the next chip layer, since layer transferring is not a time sensitive operation.</p><h4 dir="ltr">Because this scaling path is parallel and fast it could take just a few hours to complete the cycle, and importantly the cycle can be operated continuously.</h4><h4 dir="ltr">It is worth noting that using the <b>daisy-chain</b> scaling path with the same number of chips, and a cycle time of 5-days per run, we still get <b>one </b><b>64k-mer</b><b> molecule</b><b> </b><b>out every 7.2-minutes</b> in a continuous conveyor belt style arrangement.

This is may be much faster than the parallel method.<br><br><b>Many chips can be grouped to produce the desired output volume</b></h4><h4 dir="ltr">The <b>scaling path</b> trade-off is <b>(</b><b>number of </b><b>chips </b>and<b> </b><b>complexity)</b> versus <b>(</b><b>time</b><b>)</b>. The chip design is unchanged either way.</h4><h4><br></h4><p dir="ltr"><b><u>... see the PDF for more Technical Discussion, Specifications Summary and Details</u></b></p><p><br></p><h3 dir="ltr"><b>License</b></h3><h4 dir="ltr"><b>TypeOneBIS Community License (TCL)</b></h4><table><tr><th><p dir="ltr">Zenodo DOI: <a href="doi.org/10.5281/zenodo.20586399" target="_blank"><code>doi.org/10.5281/zenodo.20586399</code></a></p><p dir="ltr">Figshare DOI : <a href="doi.org/10.6084/m9.figshare.3340830" target="_blank">doi.org/10.6084/m9.figshare.3340830</a></p></th></tr></table><p dir="ltr"><b>The design files are governed by the TCL. </b>The license terms are embedded in Layer 4 of each design file, in the LICENSE.txt file in the package and are available at the DOI above.

Reading, downloading, or using the design files constitutes acceptance of the TCL.</p><h3 dir="ltr"><br><b>ZIP File Package</b></h3><p dir="ltr">typeonebis_replicator_layouts_oasis_gds2_v1_01.zip</p><p dir="ltr">SHA256 checksum hash<br>f74528b16374206dd71b771fe9c3a5f10cb04001faf87e8e22f9dc141263f004<br></p><h3 dir="ltr"><b>Related Identifiers</b></h3><table><tr><th><p dir="ltr">Relation</p></th><th><p dir="ltr">Target</p></th><th><p dir="ltr">Identifier</p></th></tr><tr><td><p dir="ltr">IsSupplementTo</p></td><td><p dir="ltr">White Paper Concept DOI</p></td><td><p dir="ltr"><code>10.5281/zenodo.20504143</code></p></td></tr><tr><td><p dir="ltr">IsDocumentedBy</p></td><td><p dir="ltr">TCL Concept DOI</p></td><td><p dir="ltr"><code>10.5281/zenodo.20586399</code></p></td></tr><tr><td><p dir="ltr">References</p></td><td><p dir="ltr">Patent Application</p></td><td><p dir="ltr">Application No. a/0002/000329</p></td></tr><tr><td><p dir="ltr">IsVersionOf</p></td><td><p dir="ltr">dataset versions</p></td><td><p dir="ltr">10.5281/zenodo.22881132, 10.6084/m9.figshare.34027272</p></td></tr></table><h3 dir="ltr"><b>Language</b></h3><p dir="ltr">English</p><p><br></p><p dir="ltr"><b>Version 1.01 – Update Notes</b></p><p dir="ltr">Re-generated the SHA256 .sum files</p>