A 1.5 GS/s 13-bit partial-interleaving pipelined-SAR ADC with 1/gm load and current-biased ring amplifier

GBWPM.xlsx: This dataset represents the optimization percentages of the ring amplifier in terms of gain-bandwidth product (GBW) and phase margin (PM) before and after optimization.gm3.xlsx: This dataset shows the transconductance variations of the third-stage ring amplifier under different PVT conditions, and compares the changes in transconductance stability before and after optimization.I2.xlsx: This dataset shows the current variations of the second-stage ring amplifier under different PVT conditions, and compares the changes in second-stage current stability before and after optimization.NQY.xlsx: This dataset presents the post-layout simulation results. 1024 data points were collected for DFT analysis to simulate the ADC performance at low frequencies and near the Nyquist frequency.PM.xlsx: This dataset shows the phase margin variations of the first-stage ring amplifier after the introduction of the 1/gm load.PVT.xlsx: This dataset presents the ADC performance under different PVT conditions.RESULTS.xlsx: This dataset shows the ADC performance variations under different input frequencies and sampling rates.transcomp.xlsx: This dataset compares the transient variations of the 1/gm load.