Benchmark circuits for clock scheduling and synthesis (Version 3)

ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results. ISPD&rsquo;10, pages 143&ndash;143, 2010.<br /> [4] J. G. Xi and W. W.-M. Dai. Useful-skew clock routing with gate sizing for low power design.

DAC &rsquo;96, pages 383&ndash;388, 1996.<br /> [5] OpenCores. opencores.net/.<br /> [6] R. Ewetz, S. Janarthanan, C.-K. Koh. Construction of Reconfigurable Clock Trees for MCMM designs. DAC&#39;15, 2015.<br /> [7] R. Ewetz, C.-K Koh, Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Reduction, TODAES, 2016.<br /> [8]&nbsp; R. Ewetz and C.-K. Koh.

MCMM clock tree optimization based on slack redistribution using a reduced slack graph. ASP-DAC&#39;16, pages 366-371, 2016.<br /> [9]&nbsp; R. Ewetz, C. Tan, and C.-K. Koh. Construction of latency-bounded clock trees.

ISPD &#39;16, 2016.<br /> [10] R. Ewetz and C.-K. Koh. Clock Tree Construction based on Arrival Time Constraints. ISPD&#39;17, 2017.<br /> [11] R. Ewetz, A Clock Tree Optimization Framework with Predictable timing Quality, DAC&#39;17, 2017.</p> <p>&nbsp;</p> <p>&nbsp;</p>