Workload-aware timing error prediction and mitigation via lightweight neural networks and algorithm-architecture co-design.

Using error-aware control and approximate-computing strategies, the proposed solutions target reliable, energyefficient operation in resource-constrained environments. Chapters 1 and 2 introduce the problem space and background—covering timing-error mechanisms, VOS, approximation, and artificial intelligence (AI)/machine learning (ML)-assisted mitigation—together with the datasets, methodology, and evaluation frameworks used throughout the thesis.<br><br>Chapter 3 develops a circuit-/microarchitectural-level view of how timing errors emerge and propagate in a floating-point multiplier (FPM) under reduced voltage.

Through path shaping, critical-path isolation, and operand-aware truncation, additional timing slack is created and error-prone operations are confined, establishing a safe baseline for low-voltage operation. This analysis sets up a cross-layer perspective that links circuit behavior, software ML modeling, and hardware realization.<br><br>Building on these insights, Chapter 4 reframes the problem from static margins to learned risk estimation.

It introduces lightweight, workload-aware predictors that operate online, integrate efficiently in system-on-chips (SoCs), and guide runtime voltage/frequency control so that timing violations are avoided while power is reduced. This transition—from redesigning datapaths to learning their failure behavior—establishes a unified flow for prediction-driven DVFS/VOS.<br><br>Chapter 5 (ePredictNet) refines the hardware realization of the online predictor using compressed neural models mapped to compact logic via LogicNets (truthtable–style netlists/RTL).

Compared to the previous chapter’s FPGA-mapped binary neural network (BNN)s, the LogicNets variant removes multipliers/digital signal processings (DSPs) and deep accumulators, yielding lower implementation overhead and higher achievable clock rates while preserving interfaces and runtime policies. The result is a streamlined, drop-in block that tightly couples to the circuit and closes the loop between software ML training and hardware realization in a single cross-layer pipeline.<br><br>Finally, Chapter 6 (ePredBitNet) advances from instruction-level prediction to explicit bit-level classification, recasting the task as a unified multi-head model realized directly in hardware for low-latency, streaming deployment.

The predicted bit mask enables lightweight correction and safety-oriented policies, while retaining the option to recover instruction-level flags. Altogether, the thesis progresses from background and circuit techniques to learned, hardware-embedded prediction and correction, demonstrating that ML-assisted control can safely unlock additional VOS headroom in modern SoC designs.<br><br><i>Thesis is embargoed until 31 July 2028.</i>