Research status and prospects of cryogenic storage for superconductor digital computing

However, compared to mature superconducting logic technologies, high-performance, scalable cryogenic memory technologies remain relatively underdeveloped, becoming a critical bottleneck restricting the development of superconducting digital computing systems.

This paper systematically reviews the research progress and architecture of cryogenic memory technologies. First, we analyze the core challenges faced in memory design under cryogenic conditions, including compatibility issues with superconducting logic circuits and storage density bottleneck. Subsequently, from the perspective of memory hierarchy, we focus on reviewing superconducting shift registers, cache based on superconducting matrix random-access memory, and main memory schemes based on cryo-CMOS, and compares the advantages and disadvantages of different technical approaches in terms of speed, density, power consumption, and scalability.