Manuscript

In this work, we investigate Scurve engineering for a unique ferroelectric-on-top (FE-o-T) negative-capacitance (NC) CFET through calibrated numerical simulations to assess its potential for ultra-low-power computing and supply-voltage scaling. Our results reveal that proper design of the CFET-to-ferroelectric aspect ratio and ferroelectric thickness is critical for capacitance matching and internal voltage amplification.

By employing an aspect ratio of 8 with a ferroelectric thickness of 6 nm, the proposed hysteresis-free FE-o-T NC-CFET achieves a room-temperature subthreshold swing of ~30 mV/dec, a ~55% reduction in supply voltage compared with the baseline CFET, and effectively suppressed short-channel effects including drain induced barrier lowering and off current. The presented design insights may facilitate the development of energy-efficient logic technologies for future computing.