On-board Data Transmission Configuration Scheme Supporting In-orbit Reconfiguration

 The core of this configuration scheme consists of two Field-Programmable Gate Arrays (FPGA) for configuration management and signal processing,magnetic random access memory (MRAM),controller area network (CAN),and FLASH.The signal processing FPGA demodulates and performs frame synchronization on the received uplink signal and transmits the data to the configuration management FPGA.The configuration management FPGA utilizes the high-speed writing feature of MRAM to cache the valid data frames and controls the data flow based on the frame identification bits.FLASH adopts a dual-zone design of firmware area and reconfiguration area,and through CAN bus instructions,switches the working program loading area of the signal processing FPGA,enabling the data transmission system to have the ability to reconfigure in case of abnormal situations.